The packaging of power devices is critical to device and system performance. Low resistance and low inductance connections are desirable for device terminals such as the source and drain terminals of a transistor or the anode and cathode terminals of a diode.
FIG. 1 depicts a cross-section view of a prior art high-voltage transistor 10 having a vertical structure with an unpatterned backside metallization that serves as a drain pad 12. Examples of such vertical devices include double-diffused metal oxide semiconductor (DMOS) transistors, insulated gate bipolar transistors (IGBTs), and junction field effect transistors (JFETs). These devices include a die 14 with a substrate 16 and an epitaxial layer 18 that are conductive. As a result, a through wafer via is not required. Moreover, a die attach process is provided with a large area, low resistance, and high current connection to the drain pad 12. Further still, a gate bond pad 20 and a source bond pad 22 are located on a frontside 24. A gate current is typically much less than a source current. Thus, the majority of the frontside 24 is usable for the source bond pad 22. A resulting large pad area available to the source bond pad 22 enables a low-cost, high current connection using large diameter wires, ribbons, or clips. A further advantage of the large pad area is that only a few large area bonds to the source bond pad 22 are required to carry a maximum device current. Another advantage is that the die 14 is also in good thermal contact with the substrate, which assists with heat dissipation.
In contrast to vertical power devices, gallium nitride (GaN) high electron mobility transistors (HEMTs) are lateral devices. As shown in FIG. 2 depicting a bond pad layout for a GaN device 26, GaN HEMTs can have a first gate pad 28, a second gate pad 30 along with both a source pad 32 and a drain pad 34 on a die front surface 36. To minimize die area, the source pad 32 and the drain pad 34 both have dimensions that are minimized. As a result of their minimized dimensions, the source pad 32 and the drain pad 34 of GaN HEMTs only provide enough space for small diameter bond wires such as source bond wires 38 and drain bond wires 40. A typical diameter for a bond wire using gold (Au) is about 25.4 μm (1 mil). As such, a typical 1200 V class GaN device in a standard TO-247 package can require between 20 and 30 bond wires on both the source pad 32 and the drain pad 34. Not only does this many bond wires add a significant packaging cost, but bond wires have significant inductance which can have a negative effect on the switching characteristics of the GaN device 26. Larger diameter bond wires, ribbons, or clips typically require a relatively large landing area that undesirably and significantly increases total die area of the GaN device 26. Another packaging option is a flip-chip process that attaches a die to a substrate using metallic bumps that are fabricated onto bond pads. However, in this case, the die is in poor thermal contact with the substrate, which results in a high thermal resistance and poor performance at elevated temperature. What is needed is an alternative structure for GaN devices such as transistors and diodes that reduces the cost and complexity of die assembly without introducing the aforementioned problems.